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用户模块数据表:Delta Sigma ADC Datasheet DelSig V 1.50 (CY8C29xxx, CYC8C24x94, CY7C64215, CY8CLED04/16, CY8CLED0xD, CY8CLED0xG, CY8CTST120, CY8CTMG120, CY8CTMA120, CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28x43, CY8C28x52) | Cypress Semiconductor

用户模块数据表:Delta Sigma ADC Datasheet DelSig V 1.50 (CY8C29xxx, CYC8C24x94, CY7C64215, CY8CLED04/16, CY8CLED0xD, CY8CLED0xG, CY8CTST120, CY8CTMG120, CY8CTMA120, CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28x43, CY8C28x52)

最近更新: 
2013 年 6 月 04 日
版本: 
1.50

功能和概述

  • 6-bit resolution with 32X oversampling to 14-bit resolution with 256X oversampling
  • 数据为无符号或有符号 2 的补码格式
  • 最大采样率为 65,500 sps(在 6 位分辨率情况下)、7812 sps(在 14 位分辨率情况下)
  • Sinc2 filter fully implemented in hardware reduces CPU overhead and anti-alias requirements
  • 1st-Order or 2nd-Order modulator, user selectable
  • 内部和外部参考选项所定义的输入范围
  • Optional synchronized PWM Output

The DelSig is an integrating converter, requiring from 32 to 256 integration cycles to generate a single output sample. Changing multiplexed inputs, invalidates the first two samples following the change.