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赛普拉斯推迟了 ARM® Cortex™-M3/PSoC® 设计挑战赛第一阶段的最后期限 | 赛普拉斯半导体

赛普拉斯推迟了 ARM® Cortex™-M3/PSoC® 设计挑战赛第一阶段的最后期限

最近更新: 2011 年 1 月 11 日

New Deadline for Schematics and Abstracts now 2011 年 1 月 24 日
to Accommodate Exceptional Demand

San Jose, Calif., 2010 年 1 月 12 日- Cypress Semiconductor Corp. (Nasdaq: CY), today extended the deadline for it’s ARM® Cortex™-M3/ PSoC® 5 Design Challenge. In order to accommodate exceptional demand, participants now have until 2011 年 1 月 24 日 to complete stage one of the challenge. The design challenge aims to find the most innovative and useful designs from the millions of possibilities available to designers using the Cypress PSoC 5 architecture powered by the ARM Cortex-M3 processor.

A total of over $10,000 in cash and prizes will be awarded throughout the contest, including the $2,500 Grand Prize. More information, including how to enter the contest and how to become a judge, as well as lively interaction from participants and the engineering community is available at https://www.cypress.com/go/challenge.

Judging of the contest entries will be done in three stages:

  • Stage 1 – 2010 年 11 月 10 日 to 2011 年 1 月 31 日 - Designers will submit schematic block diagrams and abstracts of their ideas. From these entries, the top 100 will be selected, each of which will be awarded a free PSoC 5 Development Kit.
  • Stage 2 – 2011 年 1 月 31 日 to 2011 年 4 月 4 日 - The first round winners will then submit a video of their completed designs, along with a project file created in Cypress’s PSoC Creator IDE. From this group, four winners from the following categories will be selected and awarded: $1,000: Best Analog Design, Best Digital Design, Best PSoC Creator Component Design, and the Community Choice Design as selected by popular vote of the over 20,000 members of the Cypress Design Community.
  • Stage 3 – 2011 年 4 月 4 日 to 2011 年 5 月 3 日 - The Grand Prize will be selected from the four winning designs by an all-star panel of judges, including Cypress President and CEO, T.J. Rodgers; ARM Director of Enterprise and Embedded Solutions, Ian Ferguson; and Brian Fuller, Chief Product Strategist for EE Times.

“We’re pleased to see so much interest generated by this exciting contest,” said Matt Branda, Director of PSoC Platform Marketing. “We’re hopeful that even more engineers will be able to participate and truly make this contest competitive.”

Enter today at https://www.cypress.com/go/challenge.

About PSoC 5
The PSoC 5 architecture integrates a 32-bit ARM Cortex™-M3 core with high-precision programmable analog including 12-bit to 20-bit ADCs, digital logic libraries full of dozens of drop-in peripherals, best-in-class power management and rich connectivity resources. The PSoC Creator IDE introduces a unique schematic-based design methodology along with fully tested, pre-packaged analog and digital peripherals easily customizable through user-intuitive wizards and APIs to meet specific design requirements. More information on the PSoC platform is available at https://www.cypress.com/go/psoc.

关于赛普拉斯
赛普拉斯提供各种高性能、混合信号、可编程解决方案,为客户产品能够快速上市赢得时间并提供卓越的系统价值。赛普拉斯的产品包括其旗舰产品 PSoC® 可编程片上系统系列及其衍生产品,比如 PowerPSoC® 高压和 LED 照明解决方案、CapSense® 触摸感应以及 TrueTouch™ 触摸屏解决方案。赛普拉斯是 USB 控制器领域的全球领先者,它所拥有的高性能 West Bridge® 解决方案可加强多媒体手机的连接性并提高其性能。赛普拉斯同时在高性能存储器和可编程计时设备方面处于领先地位。Cypress serves numerous markets, including consumer, mobile handsets, computation, data communications, automotive, industrial, and military. Cypress trades on the Nasdaq Global Select Market under the ticker symbol CY. Visit Cypress online at https://www.cypress.com.

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Cypress, the Cypress logo, PSoC, PowerPSoC, CapSense and West Bridge are registered trademarks and PSoC Creator and TrueTouch are trademarks of Cypress Semiconductor Corp. All other trademarks are property of their owners.

 

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