CY14V101NA-BA45XI | 赛普拉斯半导体

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CY14V101NA-BA45XI
Status: 生产中

数据手册

(pdf, 906.56 KB) RoHS PB Free
(pdf, 626.36 KB) RoHS PB Free
(pdf, 946.87 KB) RoHS PB Free

CY14V101NA-BA45XI

合格汽车
最高工作温度 (°C)85
最高工作电压 (V)3.60
最低工作温度 (°C)-40
最低工作电压 (V)2.70
Part Family并行 nvSRAM
Tape & Reel

Pricing & Inventory Availability

1-9 unit Price* 10-24 unit Price* 25-99 unit Price* 100-249 unit Price* 250-999 unit Price* 1000+ unit Price*
$24.55 $21.78 $20.46 $19.14 $18.08 $16.90
Availability Quantity Ships In Buy from Cypress Buy from Distributors
Out of Stock 0 Please click here to check lead times

Packaging/Ordering

工具包
BGA
No. of Pins
48
Package Dimensions
393 L x 1.2 H x 236 W (Mils)
Package Weight
119.15 (mgs)
Package Cross Section Drawing
Package Carrier
TRAY
Package Carrier Drawing / Orientation
Standard Pack Quantity
2990
Minimum Order Quantity (MOQ)
299
Order Increment
299
Estimated Lead Time (days)
56
HTS Code
8542.32.0041
ECCN
ECCN Suball
EAR99

Quality and RoHS

Moisture Sensitivity Level (MSL)
3
Peak Reflow Temp. (°C)
符合有害物质限制 (RoHS) 标准
无铅
Lead/Ball Finish
Sn/Ag/Cu

Package Qualification Report

技术文档

应用笔记 (10)

产品变更通知 (PCN) (7)

2020 年 5 月 7 日
Qualification of BKK as an additional assembly site for select 48 & 121 ball grid array (BGA)
2020 年 4 月 14 日
Serial Number Addition to Top Mark for Select Flash and SRAM Parts at Cypress Bangkok
2018 年 5 月 29 日
Qualification of Cypress Philippines as an Additional Assembly Site for select 48BGA products
2017 年 11 月 09 日
Planned Qualification of Spansion Manufacturing Sites for Cypress Products
2017 年 10 月 31 日
Q2, 2012 - Q4, 2013 Horizon Report
2017 年 10 月 30 日
Q1, 2012 - Q2, 2013 Horizon Report
2017 年 10 月 24 日
Qualification of Copper Wire Bonds for Ball Grid Array (BGA) Products

Product Information Notice (PIN) (4)

2020 年 6 月 10 日
Manufacturing Label and Packing Configuration Standardization
2020 年 4 月 14 日
Addendum to PIN195102 - Manufacturing Label and Packing Configuration Standardization
2017 年 11 月 06 日
Changes to Cypress Address Labels
2017 年 11 月 06 日
Improvement of Cypress Minnesota Back-End-of-Line Integration for 130nm SONOS Product Families

Verilog (1)

2011 年 1 月 26 日

VHDL (1)

2011 年 1 月 26 日

IBIS (1)

2010 年 5 月 10 日