CY7C1370D-200BZC | 赛普拉斯半导体

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CY7C1370D-200BZC
Status: 废弃

CY7C1370D-200BZC

架构NoBL, Pipeline
合格汽车
密度 (Kb)18432
Density (Mb)18
频率 (MHz)200
最高工作温度 (°C)70
Max. Operating VCCQ (V)3.60
最高工作电压 (V)3.63
最低工作温度 (°C)0
Min. Operating VCCQ (V)2.40
最低工作电压 (V)3.14
组织 (X x Y)512Kb x 36
Tape & Reel
温度分类商用

Pricing & Inventory Availability

1-9 unit Price* 10-24 unit Price* 25-99 unit Price* 100-249 unit Price* 250-999 unit Price* 1000+ unit Price*
$35.67 $31.81 $29.50 $27.18 $26.22 $25.06
Availability Quantity Ships In Buy from Cypress Buy from Distributors
Out of Stock 0 Please click here to check lead times

Packaging/Ordering

工具包
BGA
No. of Pins
165
Package Dimensions
591 L x 1.4 H x 512 W (Mils)
Package Weight
501.06 (mgs)
Package Cross Section Drawing
Package Carrier
TRAY
Standard Pack Quantity
1360
Minimum Order Quantity (MOQ)
136
Order Increment
136
Estimated Lead Time (days)
182
HTS Code
8542.32.0041
ECCN
(B.2.A.)
ECCN Suball
3A991

Quality and RoHS

Moisture Sensitivity Level (MSL)
3
Peak Reflow Temp. (°C)
符合有害物质限制 (RoHS) 标准
无铅
Lead/Ball Finish
Sn/Pb

封装材料声明

技术文档

应用笔记 (3)

产品变更通知 (PCN) (8)

2018 年 5 月 28 日
Qualification of Cypress Manufacturing Limited as an additional assembly site for 165-FBGA. This supersedes the Advanced PCN No. 060981
2018 年 5 月 28 日
Qualification of JEDEC Shipping Tray for Sync and QDR SRAM products in 165 FBGA package
2018 年 5 月 28 日
Subject: Qualification of 165 ball 13x15x1.4mm BGA Pb-Free and SnPb Solder Ball Packages
2018 年 5 月 28 日
Qualification of Advanced Interconnect Technologies (AIT), as an alternate assembly site for 165 ball 13x15x1.4mm BGA Packages Using SnPb Solder Balls
2018 年 5 月 27 日
Shipping Label Upgrade
2017 年 10 月 31 日
Q2, 2012 - Q4, 2013 Horizon Report
2017 年 10 月 30 日
Q1, 2012 - Q2, 2013 Horizon Report
2017 年 10 月 24 日
Qualification of Copper Wire Bonds for Ball Grid Array (BGA) Products

Product Termination Notice (PTN) (1)

2017 年 11 月 09 日
December 2012 Product Obsolescence Notification

Verilog (1)

2010 年 11 月 22 日

IBIS (1)

2010 年 11 月 22 日

BSDL (1)

2008 年 11 月 13 日

VHDL (1)

2008 年 11 月 13 日