CY7C53120E4-40SXI | 赛普拉斯半导体

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CY7C53120E4-40SXI
Status: 生产中

数据手册

(pdf, 539.48 KB) RoHS PB Free

CY7C53120E4-40SXI

合格汽车
闪存 (KB)4
Max. Input Clock (MHz)40
最高工作温度 (°C)85
最高工作电压 (V)5.00
最低工作温度 (°C)-40
最低工作电压 (V)5.00
ROM (KB)12
Tape & Reel

Pricing & Inventory Availability

1-9 unit Price* 10-24 unit Price* 25-99 unit Price* 100-249 unit Price* 250-999 unit Price* 1000+ unit Price*
联系销售人员
Availability Quantity Ships In Buy from Cypress Buy from Distributors
Out of Stock 0 Please click here to check lead times

Packaging/Ordering

工具包
SOP
No. of Pins
32
Package Dimensions
810 L x 0 H x 450 W (Mils)
Package Weight
1 340.00 (mgs)
Package Cross Section Drawing
Package Carrier
TUBE
Package Carrier Drawing / Orientation
Standard Pack Quantity
125
Minimum Order Quantity (MOQ)
125
Order Increment
125
Estimated Lead Time (days)
91
HTS Code
8542.31.0001
ECCN
ECCN Suball
EAR99

Quality and RoHS

Moisture Sensitivity Level (MSL)
3
Peak Reflow Temp. (°C)
符合有害物质限制 (RoHS) 标准
无铅
Lead/Ball Finish
Pure Sn

技术文档

应用笔记 (1)

产品变更通知 (PCN) (16)

2020 年 7 月 14 日
Transfer of Assembly Operations to Greatek Electronics Inc. for Select 32-Lead SOIC Package.
2020 年 5 月 8 日
Notice of plan to transfer package manufacturing from Cypress Philippines to Jiangsu Changjiang Electronics Technology Co., Ltd. (JCET).
2018 年 5 月 28 日
Transfer of package manufacturing from Cypress Philippines to Jiangsu Changjiang Electronics Technology Co., Ltd. (JCET) for select products
2018 年 5 月 28 日
Changes to Minimum Order Quantity (MOQ) and Order Increment (OI) values on various Cypress Products.
2018 年 5 月 28 日
Changes to Minimum Order Quantity (MOQ) and Order Increment (OI) values on various Cypress Products
2018 年 5 月 28 日
Add Alternate Assembly Site for SOIC150mils Pb-Free
2018 年 5 月 28 日
Qualification of Cypress Minnesota as Alternate Wafer Fabrication Facility for Neuron® Chip Network Processor Products
2018 年 5 月 28 日
Qualification of KEG6000DA and KEG3000DA Green Mold Compound for 32 leads, Lead-free and standard, 450 mil body size, SOIC Packages Assembled at Cypress
2018 年 5 月 27 日
Change in Tube Bundling Ship Process
2018 年 5 月 27 日
Shipping Label Upgrade
2018 年 5 月 27 日
Correction to Affected Devices in PCN#071577: Qualification of 0.9-mil Au wire diameter for CCD and MID devices assembled at CML
2018 年 5 月 27 日
Qualification of 0.9-mil Au wire diameter for CCD and MID devices assembled at CML
2017 年 11 月 09 日
Planned Qualification of Spansion Manufacturing Sites for Cypress Products
2017 年 10 月 31 日
Q2, 2012 - Q4, 2013 Horizon Report
2017 年 10 月 30 日
Q1, 2012 - Q2, 2013 Horizon Report
2017 年 10 月 25 日
Qualification of Copper Palladium Wire Bonds for Select Lead Frame Products at JCET China

Advanced Product Change Notice (APCN) (4)

2020 年 8 月 23 日
Q32020 Horizon Report Update
2020 年 4 月 14 日
Q419 Horizon Report Update
2018 年 5 月 27 日
Advance Notification - Planned Changes to MoBL-USB TX3LP18
2018 年 5 月 27 日
Advance Notification - Transfer of Specific Product Manufactured by Cypress Semiconductor Texas to Cypress Manufacturing Minnesota

Product Information Notice (PIN) (6)

2020 年 7 月 28 日
USB Products Failure Analysis Policy Change
2020 年 6 月 10 日
Manufacturing Label and Packing Configuration Standardization
2020 年 4 月 14 日
Addendum to PIN195102 - Manufacturing Label and Packing Configuration Standardization
2017 年 11 月 07 日
Qualification of Test 25 (Austin, Texas) as an Additional Wafer-Level Test Location.
2017 年 11 月 06 日
Changes to Cypress Address Labels
2017 年 11 月 06 日
Addendum to PIN 135258 - Qualification of JCET as an additional Test and Finish Location for Cypress Products