CY8C3246PVI-122 | 赛普拉斯半导体

You are here

CY8C3246PVI-122
Status: 生产中

数据手册

(pdf, 4.13 MB) RoHS PB Free
(pdf, 3.09 MB) RoHS PB Free

CY8C3246PVI-122

Development KitCY8CKIT-001
合格汽车
Boost Converter (Volts)0.5
CPU Core8051
CapSense
专用模数转换器(#_ 最大分辨率 @ 采样速率)DelSig (1, 12-bit @ 192 ksps)
专用数模转换器(编号_最大分辨率 @ 采样速率)(1、8-bit @ 8 msps)
EEPROM (KB)2
闪存 (KB)64
JTAG and Si ID0x1E07A069
LCD 直接驱动(是/否)
最高工作频率 (MHz)50
最高工作温度 (°C)85
最高工作电压 (V)5.50
最低工作温度 (°C)-40
最低工作电压 (V)1.71
No. of CAN Controllers0
No. of DMA Channels24
No. of Dedicated Comparators2
No. of Dedicated Digital Filter Blocks0
No. of Dedicated I2C1
No. of Dedicated OpAmps0
No. of Dedicated SPI0
No. of Dedicated Timer/Counter/PWM Blocks4
No. of Dedicated UART0
GPIO 编号25
可编程模拟模块编号0
可编程通用数字模块编号24
No. of USB IO0
SRAM (KB)8
Tape & Reel
USB (Type)

Pricing & Inventory Availability

1-9 unit Price* 10-24 unit Price* 25-99 unit Price* 100-249 unit Price* 250-999 unit Price* 1000+ unit Price*
$4.23 $4.06 $3.88 $3.70 $3.52 $3.23
Availability Quantity Ships In Buy from Cypress Buy from Distributors
Out of Stock 0 Please click here to check lead times

Packaging/Ordering

工具包
SOP
No. of Pins
48
Package Dimensions
625 L x 2.3 H x 295 W (Mils)
Package Weight
650.23 (mgs)
Package Cross Section Drawing
Package Carrier
TUBE
Package Carrier Drawing / Orientation
Standard Pack Quantity
600
Minimum Order Quantity (MOQ)
60
Order Increment
60
Estimated Lead Time (days)
140
HTS Code
8542.31.0001
ECCN Suball
3A991.A.3

Quality and RoHS

Moisture Sensitivity Level (MSL)
3
Peak Reflow Temp. (°C)
符合有害物质限制 (RoHS) 标准
无铅
Lead/Ball Finish
Ni/Pd/Au

技术文档

应用笔记 (21)

2020 年 5 月 29 日

产品变更通知 (PCN) (3)

2020 年 11 月 11 日
Transfer of Assembly Operations to Greatek Electronics Inc. for Select 48-Lead SSOP Package
2017 年 10 月 31 日
Q2, 2012 - Q4, 2013 Horizon Report
2017 年 10 月 30 日
Q1, 2012 - Q2, 2013 Horizon Report

Advanced Product Change Notice (APCN) (1)

2020 年 8 月 23 日
Q32020 Horizon Report Update

Product Information Notice (PIN) (8)

2020 年 6 月 10 日
Manufacturing Label and Packing Configuration Standardization
2020 年 4 月 14 日
Addendum to PIN195102 - Manufacturing Label and Packing Configuration Standardization
2017 年 11 月 07 日
PSoC Programmer Upgrade for PSoC 3 Family of Products
2017 年 11 月 06 日
Qualification of Manufacturing and Design Changes for PSoC 3 Products
2017 年 11 月 06 日
Changes to Cypress Address Labels
2017 年 11 月 06 日
Addendum to PIN 135258 - Qualification of JCET as an additional Test and Finish Location for Cypress Products
2017 年 11 月 06 日
Improvement of Cypress Minnesota Back-End-of-Line Integration for 130nm SONOS Product Families
2017 年 10 月 26 日
Datasheet changes-PSoC 3 Products

边界扫描 BSDL (2)

2012 年 12 月 10 日
2011 年 4 月 06 日