CY8C3246PVI-122 | 赛普拉斯半导体
CY8C3246PVI-122
Development Kit | CY8CKIT-001 |
合格汽车 | 否 |
Boost Converter (Volts) | 0.5 |
CPU Core | 8051 |
CapSense | 是 |
专用模数转换器(#_ 最大分辨率 @ 采样速率) | DelSig (1, 12-bit @ 192 ksps) |
专用数模转换器(编号_最大分辨率 @ 采样速率) | (1、8-bit @ 8 msps) |
EEPROM (KB) | 2 |
闪存 (KB) | 64 |
JTAG and Si ID | 0x1E07A069 |
LCD 直接驱动(是/否) | 是 |
最高工作频率 (MHz) | 50 |
最高工作温度 (°C) | 85 |
最高工作电压 (V) | 5.50 |
最低工作温度 (°C) | -40 |
最低工作电压 (V) | 1.71 |
No. of CAN Controllers | 0 |
No. of DMA Channels | 24 |
No. of Dedicated Comparators | 2 |
No. of Dedicated Digital Filter Blocks | 0 |
No. of Dedicated I2C | 1 |
No. of Dedicated OpAmps | 0 |
No. of Dedicated SPI | 0 |
No. of Dedicated Timer/Counter/PWM Blocks | 4 |
No. of Dedicated UART | 0 |
GPIO 编号 | 25 |
可编程模拟模块编号 | 0 |
可编程通用数字模块编号 | 24 |
No. of USB IO | 0 |
SRAM (KB) | 8 |
Tape & Reel | 否 |
USB (Type) | 无 |
Pricing & Inventory Availability
1-9 unit Price* | 10-24 unit Price* | 25-99 unit Price* | 100-249 unit Price* | 250-999 unit Price* | 1000+ unit Price* |
---|---|---|---|---|---|
$4.23 | $4.06 | $3.88 | $3.70 | $3.52 | $3.23 |
Packaging/Ordering
工具包
No. of Pins
48
Package Dimensions
625 L x 2.3 H x 295 W (Mils)
Package Weight
650.23 (mgs)
Package Cross Section Drawing
Package Carrier
TUBE
Package Carrier Drawing / Orientation
Standard Pack Quantity
600
Minimum Order Quantity (MOQ)
60
Order Increment
60
Estimated Lead Time (days)
140
HTS Code
8542.31.0001
ECCN Suball
3A991.A.3
Quality and RoHS
Moisture Sensitivity Level (MSL)
3
Peak Reflow Temp. (°C)
260 (Cypress Reflow Profile)
符合有害物质限制 (RoHS) 标准
无铅
是
Lead/Ball Finish
Ni/Pd/Au
Marking
IPC 1752 材料成分声明
Last Update: 2020 年 5 月 19 日
技术文档
应用笔记 (21)
2020 年 7 月 01 日
AN2099 - PSoC® 1, PSoC 3, PSoC 4, and PSoC 5LP - Single-Pole Infinite Impulse Response (IIR) Filters
2020 年 5 月 28 日
2018 年 10 月 11 日
2018 年 10 月 09 日
产品变更通知 (PCN) (3)
2020 年 11 月 11 日
Transfer of Assembly Operations to Greatek Electronics Inc. for Select 48-Lead SSOP Package
Advanced Product Change Notice (APCN) (1)
Product Information Notice (PIN) (8)
2020 年 4 月 14 日
Addendum to PIN195102 - Manufacturing Label and Packing Configuration Standardization
2017 年 11 月 06 日
Addendum to PIN 135258 - Qualification of JCET as an additional Test and Finish Location for Cypress Products
2017 年 11 月 06 日
Improvement of Cypress Minnesota Back-End-of-Line Integration for 130nm SONOS Product Families