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异步 SRAM | 赛普拉斯半导体


Ultra-Reliable Asynchronous SRAMs

With the performance to serve a wide variety of high reliability industrial, communication, data processing, medical, consumer and military applications, Fast and Micropower (MoBL®) SRAM devices are available with on-chip ECC. These devices are form-fit-function compatible with older generation Asynchronous SRAMs. This allows you to improve system reliability without investing in PCB re-design.

  • High reliability: Soft-Error Rate < 0.1FIT/Mbit
  • ERR pin to indicate single-bit errors
  • Density options: 4-Mbit, 8-Mbit, 16-Mbit
  • Fast access time: 10ns (FAST)
  • Ultra-low standby current: 8.7μA (4-Mbit MoBL®)
  • Bus-width configurations: x8, x16 and x32
  • 宽广的工作电压范围:1.8-5.0V
  • Industrial and Automotive temperature grades


Cypress is the first SRAM manufacturer to offer a new family of devices that combines the access time of Fast Asynchronous SRAM with a unique ultra-low-power sleep mode (PowerSnooze™). Fast SRAM with PowerSnooze eliminates the tradeoff between performance and power consumption in Asynchronous SRAM applications. In this new family of devices, the best features of existing family of products are achieved through the provision of a novel ultra-low-power sleep mode called PowerSnooze. PowerSnooze is an additional operating mode to standard Asynchronous SRAM operating modes (Active, Standby, and Data-Retention). Deep sleep pin (DS#) enables switching of the device between the high performance active mode and the ultra-low-power PowerSnooze mode. With deep sleep current as low as 15 μA on 4-Mbit devices, Fast SRAM with PowerSnooze combines the best features of Fast and Micropower SRAM in a single device.

Asynchronous SRAM Technology Enhancements

Error Correcting Code (ECC)
Cypress’s latest generation Asynchronous SRAM devices use (38,32) hamming code ECC for single-bit error detection and correction. The hardware ECC block in Cypress’ ultra-reliable Asynchronous SRAMs performs all ECC related functions in line, without user intervention.

Multi-bit Interleaving
Higher energy extraterrestrial radiation can flip multiple adjacent bits, leading to multi-bit errors. The single-bit error detection and correction capability of Error Correcting Code is supplemented by a bit-interleaving scheme to prevent the occurrence of multi-bit errors.

Together, these features provide significant improvement in Soft Error Rate (SER) performance, resulting in industry leading FIT rates of less than 0.1 FIT/Mbit.

特性 Fast Micropower SRAM with ECC
Access time 10ns 45ns 10ns, 45ns
Density 256Kb-32Mb 256Kb-64Mb 4Mb-16Mb
On-Chip Error Correction Code (ECC)
Data Width X8, X16, X32 X8, X16 X8, X16, X32
Voltage 1.8V, 3V, 5V 1.8V, 3V, 5V 1.8V, 3V, 5V
Temperature Grade 工业
Document Type Fast Micropower SRAM with ECC
产品路线图 1 1 1
应用手册 1 2 2
数据表 56 57 24
模型 137 80 3
其他资源 4   1
产品手册 1 1 1
产品变更通知 (PCN) 7 3  
产品概览 1   2
Product Termination Notice (PTN) 2    
资质报告 48 43  
技术文章 4    
白皮书 1 1  
知识库文章 61

Memory for wide variety of applications

Asynchronous SRAMs with ECC are suitable for a wide variety of industrial, medical, commercial, automotive and military applications that require the highest standards of reliability and performance. Fast SRAMs are an ideal choice in networking applications such as switches and routers, IP-phones, test equipment and automotive electronics. MoBL® SRAMs are used in high-performance, battery powered and battery-backed solutions across a range of application segments, like PLCs, Multifunction Printers and Implantable medical devices.

Industrial controllers
      Multi-Functional printers
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