PSoC® 3 是真正的可编程嵌入式片上系统，在单个芯片上集成了可配置模拟和数字外设功能、存储器和微控制器。现在我们创新的 PSoC 3 架构可通过以下方法改善性能：
- 集成了高精度 20 位分辨率模拟
- 基于 PLD 的可编程逻辑
- 单周期 8051 内核，最多 67 MHz
PSoC 3 is now available in Chip Scale Packages (CSP) allowing you to design with the flexibility of PSoC in space constrained and small form factor applications like wearables, fitness products, and mobile devices.
The PSoC® architecture consists of configurable analog and digital blocks, a CPU subsystem and programmable routing and interconnect. PSoC lets you plug in predefined and tested IP from the PSoC library of functions, or code your own. Either way, you have the flexibility to build innovation and competitive advantage into your products.
Programable Routing & Interconnect
This frees you to re-route signals to userselected pins, shedding the constraints of a fixed-peripheral controller. In addition, global buses allow for signal multiplexing and logic operations, eliminating the need for a complicated digital-logic gate design.
Configurable Analog and Digital Blocks
The union of configurable analog and digital circuitry is the basis of the PSoC platform. You configure these blocks using pre-built library functions or by creating your own. By combining several digital blocks, you can create 16-, 24-, or even 32-bit wide logic resources. The analog blocks are composed of an assortment of switch capacitor, op-amp, comparator, ADC, DAC, and digital filter blocks, allowing complex analog signal flows. For a partial list of preconfigured functions included in PSoC software, see the sidebars on the next two pages. You can modify and personalize each function to your design.
PSoC offers a sophisticated CPU subsystem with SRAM , EE PROM, and flash memory, multiple core options and a variety of essential system resources including:
• Internal main and low-speed oscillator
• Connectivity to external crystal oscillator for precision, programmable clocking
• Sleep and watchdog timers
• Multiple clock sources that include a PLL
PSoC devices also have dedicated communication interfaces like I2C, Full-Speed USB 2.0, CAN 2.0, and on-chip debugging capabilities using JTAG and Serial Wire Debug. The newest members of the PSoC family offer industry-standard processors like the 8051 and Arm Cortex-M3.
Ultra Low Power
Low Power Management Solutions with PSoC 3 and PSoC 5 devices are easy to design and implement because both families were designed for power optimization. PSoC 3 and PSoC 5 devices have flexible power modes to optimize power and performance.
- Best-in-class low power specifications plus industry leading CPU speed
- World’s widest voltage range, the only device that offers full analog capability below 1.8V
- Minimizes power by offloading CPU processing using on-chip programmable logic
- Integrated peripherals reduce total system level power
- PSoC Creator software provides easy to use APIs for quick power management
- 宽广的工作电压范围：0.5V to 5.5V
- 0.8 mA at 3 MHz, 1.2 mA at 6 MHz, 6.6 mA at 48 MHz
- 1 µA sleep mode with real-time clock and low voltage detect (LVD) interrupt
- 200 nA hibernate mode with SRAM retention
||Clock Sources Available
PICU, I2C, RTC,
|XRES, LVD, WDR
Full Analog Performance Across the Entire Voltage Range
PSoC 3 and PSoC 5 are the only devices on the market to offer full analog performance down to 0.5V allowing you to not only operate off of a single cell battery, but also a solar cell.