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Using multiple devices to create a deeper array | 赛普拉斯半导体

Using multiple devices to create a deeper array


2011 年 6 月 11 日

The dual-ports must be arranged in a depth expansion configuration on the board.  Each port has its own address, control, clock, and data signals (as with any dual-port system).  The port's control signals usually include one or more chip enable signals. In depth expansion, all signals except for the chip enables are routed in parallel to the same port on each evice.  All the chip enable signals must be active to perform read or write operations to the associated port.  In depth expansion, the chip enables should be controlled so only one device is active for each port.  Note that the same device can be active for both ports, or two devices can be active for opposite ports.  In effect, each device makes up part of the total memory space and the chip enables act like extra address bits to specify which part of the memory space should be accessed from each port. Many devices have 2 chip enables, one that is active-high and one that is active-low.  This makes doubling the depth of the memory trivial.  For example, suppose two 128Kx36 dual-ports need to be arranged as a 256Kx36 dual-port.  To address 256K words, 18 address bits are needed.  Each device port has 17 address inputs, an active-high chip enable, and an active-low chip enable.  To achieve the desired configuration, the following connections should be made: Device 1: Address - System Address [16:0] CE0b - System Address [17] CE1 - Pull up to VCC Device 2: Address - System Address [16:0] CE0b - GND CE1 - System Address [17] If the dual-ports do not have active-high and active-low chip enables or more than 2 devices need to be used in depth-expansion, a decoder must be implemented in an external CPLD or FPGA.  The decoder would have n inputs and 2^n outputs, where n is the number of extra address bits and 2^n is the number of depth expanded dual-ports.